Integrated circuits are becoming more densely packed with increasing numbers of individual circuit elements. Typically, testing these circuit elements is performed by generating a test pattern and applying the test pattern to the integrated circuit using scan chains, where each scan chain includes a number of individual scan cells. Depending on the test pattern, the responses of the integrated circuit to the test pattern can provide an accurate indication of the existence or non-existence of defects or faults.
The test pattern is applied as a test vector, where the test vector is a set of bits applied to a number of scan cells in a scan chain. With a test vector loaded into the scan chain, the device being tested is stimulated. The response to the stimulus is compared to a reference vector stored in a tester. Pass/fail functionality of the device under test may be determined by this comparison.
Design for testability (DFT) features that provide for embedded testing of certain integrated circuit functions aid in the testing of the integrated circuit. Another DFT feature that can be implemented is a built-in self-test (BIST) capability. However, as the complexity of integrated circuits, such as microprocessors and application-specific integrated circuits, ASICs, increases, testing requirements also increase including the number and size of test vectors to appropriately test the integrated circuit. These enhancements in the test requirements increase both the needed testing buffer capacity and the test application time.